AMD also gave us a brief update on 45nm, stating that they have successfully produced a SRAM test wafer at 45nm.  It's very popular to produce a wafer full of SRAM chips as you're bringing up and validating any new process, since the circuits are simple enough to actually make the chips producable but complex enough to get useful feedback on your process from the test wafer. 

AMD's 45nm SRAM test wafer follows a little over 3 months after Intel demonstrated a similar 45nm test wafer.  The benchmark when producing a wafer of SRAM is how small you're able to produce each SRAM cell. At 45nm Intel was able to achieve a 0.346 square micron SRAM cell size compared to AMD's 0.370 square micron SRAM cells.  Intel's advantage in SRAM cell size is nothing new, as they have been doing so in previous process technologies as well.  The advantage in SRAM cell size is one reason why you often see Intel more eager to equip its CPUs with larger L2 caches; obviously with no on-die memory controller, Intel also often benefits much more from a larger L2 cache than AMD in the first place. 


Intel's 45nm SRAM test vehicle - 0.346 sq micron cell size

Today's update had nothing to do with Socket-AM2 or AMD's transition to DDR2, but we do have some news with regards to that as well.  As you've undoubtedly heard and maybe even seen elsewhere, AMD's AM2 platform has not been performing very well in development over these past couple of months.  Just before IDF, AM2 samples were still performing lower than their Socket-939 counterparts, which was beginning to worry us and AMD's parters a bit.  However we're excited to report that AM2 performance has finally started exceeding that of Socket-939.  The performance gains we've been hearing and seeing are generally 5% or lower at the same clock speeds using DDR2-800, but it's still very early.  The main point to take home is while the final verdict is still not out, AM2 is at least starting to look like more of an upgrade and not what we saw with Intel's DDR to DDR2 transition almost 2 years ago. 

There's still a lot that AMD does have to give us however, including a more specific roadmap of what comes after their DDR2 transition.  AMD's Phil Hester has publicly stated that once AM2 launches it will be more forthcoming with information on future architecture revisions, we can only hope so because over the past 12 months Intel has put the pressure on AMD to really start talking about the future.  

The good news today is that AMD is truly growing as a company.  By 2008 AMD hopes to be able to double its yearly shipments of microprocessors, and it's finally got manufacturing capacity to do just that.  For the past few years AMD has held technological and performance advantages over Intel, now it's time for AMD to play catchup on the manufacturing side.  AMD has a long way to go before being anywhere close to Intel's manufacturing abilities, but it is in a very good place today.

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  • Viditor - Wednesday, April 5, 2006 - link

    quote:

    Dude, you said three posts up that there aren't any estimates for production at fab 36, and here you said there are

    No, I said AMD hadn't released any estimates...this article was not from AMD.
  • fikimiki - Wednesday, April 5, 2006 - link

    Hector Ruiz said:http://www.fabtech.org/index.php?option=content&am...">Here:

    "Our latest projections average out certain factors, but we feel it is not unreasonable for Fab 36 to have 26,000wspm by the end of 2006. Then depending on a host of factors, fab capacity would be reached sometime in the 1H07."

    And because of 65nm transitions they have to lower a production output to ~17wspm. Fab36 was not designed to have smaller production output than FAB30 - for sure...

  • coldpower27 - Wednesday, April 5, 2006 - link

    26K WSPM by end of 2006? When AMD is claiming 20K WSPM by 2008, don't you find that somewhat odd?
  • Viditor - Wednesday, April 5, 2006 - link

    quote:

    26K WSPM by end of 2006? When AMD is claiming 20K WSPM by 2008, don't you find that somewhat odd?


    That would be the old numbers...AMD has increased the efficiency of their Fabs. For example, Fab30 was originally to max out at 20k wspm and now does 30k. AFAIK, AMD has not released current capacity estimates for Fab 36.
  • Questar - Wednesday, April 5, 2006 - link

    "To ameliorate some of the financial risks, AMD will not completely build out the facility just yet. As it stands now, AMD can start production on 13,000 silicon wafers a month. Enough empty space, however, exists to crank that up to 20,000 wafer starts a month. Getting to the 100 million mark will involve populating the current empty space in the 13,400-square-meter plant with equipment."

    http://news.com.com/With+new+factory%2C+AMD+ups+an...">http://news.com.com/With+new+factory%2C.../2100-10...
  • Viditor - Wednesday, April 5, 2006 - link

    It doesn't really matter, but the article is from the Grand Opening in October.
    The key point here is the number 15,000wspm. That represents (on 300mm) a doubling of capacity. By this years end, between Fab 36 and Chartered we will most likely see a tripling of capacity.
  • coldpower27 - Wednesday, April 5, 2006 - link

    Well since this article was released later, I am going to go with what is here as more accurate, I don't see any reason to beleive the Fabtech document versus what is written here.
  • defter - Wednesday, April 5, 2006 - link

    quote:

    Hector Ruiz said:Here


    No he didn't. That article contains guesses and estimates of fabtech.org and according to their page, that article is already quite old. For example they are talking about ramp starting in Q1 although shipments only began in Q2.
  • Viditor - Wednesday, April 5, 2006 - link

    quote:

    they are talking about ramp starting in Q1 although shipments only began in Q2

    Actually, the ramp began at the end of Q4 05...it takes about 3 months for shipping product after a ramp begins.
  • mesyn191 - Wednesday, April 5, 2006 - link

    Yea, I'd be suprised if we saw more than a 20% clockspeed improvement over .90 chips assumig the .65 chip is just a die shrink with no clocspeed optimizations made of course.

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