Barcelona Architecture: AMD on the Counterattack
by Anand Lal Shimpi on March 1, 2007 12:05 AM EST- Posted in
- CPUs
New Prefetcher
Prefetching is done in many areas of the system and by many different components. When NVIDIA introduced its nForce2 chipset, it stressed the ability of its intelligent prefetcher to make use of a very wide, at the time, 128-bit memory bus. More recently, when Intel introduced its Core 2 processor family it stressed the importance of its three prefetchers per core in drastically reducing perceived memory latency.
AMD's K8 core had two prefetchers per core - one instruction and one data. The Barcelona core still retains the same number of prefetchers, but improves on them. The biggest change is that the data prefetcher now brings data directly into the L1 data cache, as opposed to the L2 cache in the K8. AMD looked at the accuracy of its core prefetchers and realized that they were doing quite well, so it only made sense to prefetch into a low latency L1 and avoid polluting the L2 cache. AMD has also increased the flexibility of its L1 instruction cache prefetcher to handle two outstanding requests to any address.
At first glance it looks like Intel's prefetchers in Core 2 are greater, at least in quantity, than what AMD has planned even for Barcelona. Remember that Intel's Core 2 processor features two data and one instruction prefetcher per core, plus an additional two L2 cache prefetchers, all of which are well managed as to not eat into "demand" bandwidth. At the same time, we must keep in mind that Intel needs these prefetchers to help mask its longer trip to main memory. From a CPU perspective, the advantage here is for Intel, but as a platform the true winner is tough to determine.
Each Barcelona core gets its own set of data and instruction prefetchers, but the major improvement is that there's a new prefetcher in town - a DRAM prefetcher. Residing within the memory controller where AMD previously never had any such logic, the new DRAM prefetcher takes a look at overall memory requests and attempts to pull data it thinks will be used in the future. As this prefetcher has to contend with the needs of four separate cores, it really helps the entire chip improve performance and can do a good job of spotting trends that would positively impact all cores. The DRAM prefetcher doesn't pull data into the CPU's L2 or L3 caches either; instead it features its own buffer to avoid polluting the caches. The buffer is approximately 20 - 30 cache lines in size and happens to be the same buffer that is used for Barcelona's write bursting we mentioned on the previous page.
Prefetching is done in many areas of the system and by many different components. When NVIDIA introduced its nForce2 chipset, it stressed the ability of its intelligent prefetcher to make use of a very wide, at the time, 128-bit memory bus. More recently, when Intel introduced its Core 2 processor family it stressed the importance of its three prefetchers per core in drastically reducing perceived memory latency.
AMD's K8 core had two prefetchers per core - one instruction and one data. The Barcelona core still retains the same number of prefetchers, but improves on them. The biggest change is that the data prefetcher now brings data directly into the L1 data cache, as opposed to the L2 cache in the K8. AMD looked at the accuracy of its core prefetchers and realized that they were doing quite well, so it only made sense to prefetch into a low latency L1 and avoid polluting the L2 cache. AMD has also increased the flexibility of its L1 instruction cache prefetcher to handle two outstanding requests to any address.
At first glance it looks like Intel's prefetchers in Core 2 are greater, at least in quantity, than what AMD has planned even for Barcelona. Remember that Intel's Core 2 processor features two data and one instruction prefetcher per core, plus an additional two L2 cache prefetchers, all of which are well managed as to not eat into "demand" bandwidth. At the same time, we must keep in mind that Intel needs these prefetchers to help mask its longer trip to main memory. From a CPU perspective, the advantage here is for Intel, but as a platform the true winner is tough to determine.
Each Barcelona core gets its own set of data and instruction prefetchers, but the major improvement is that there's a new prefetcher in town - a DRAM prefetcher. Residing within the memory controller where AMD previously never had any such logic, the new DRAM prefetcher takes a look at overall memory requests and attempts to pull data it thinks will be used in the future. As this prefetcher has to contend with the needs of four separate cores, it really helps the entire chip improve performance and can do a good job of spotting trends that would positively impact all cores. The DRAM prefetcher doesn't pull data into the CPU's L2 or L3 caches either; instead it features its own buffer to avoid polluting the caches. The buffer is approximately 20 - 30 cache lines in size and happens to be the same buffer that is used for Barcelona's write bursting we mentioned on the previous page.
Facebook
Twitter
RSS
83 Comments
View All Comments
R3MF - Thursday, March 1, 2007 - link
thanks.a 2.4GHz Agena on an AM2+ mATX motherboard, sat in a tiny SUGO 03 case sounds like a very tempting proposition later on this year.
Macuser89 - Thursday, March 1, 2007 - link
Is it just me or is this article saying that AMD is copying a lot of intel's advancements. Great in depth article AT.Le Québécois - Thursday, March 1, 2007 - link
I may be wrong but I think that new CPU or GPU technologies are planned years ahead so for me it look more like they came down to the "same" conclusion on how to improve their CPU. Only Intel did it 1 year before AMD.JarredWalton - Thursday, March 1, 2007 - link
There are fundamentally only so many ways to improve processor performance, and Intel used most of them with Core 2. That AMD is using similar patterns (more buffers, better branch prediction, wider execution, etc.) isn't at all surprising. Just because the same basic principles are used, however, doesn't mean that at the transistor level there aren't significant differences and challenges to overcome.archcommus - Thursday, March 1, 2007 - link
Another great article that displays all the reasons why I read AT - lengthy, technical reviews written by educated authors that are interesting to read and to top it off, with no typing errors! I'm sure you guys use voice software to write these mammoths.I was waiting for details on Barcelona for so long and this is finally it. I have no doubt that AMD will be up to par with Intel again, but the question is, will this significantly SURPASS Core 2 offerings at the time? I hope so but it's not a definite thing yet.
The best thing is, I'm a ways into my computer engineering degree now so I can actually understand a lot of these very techincal articles!
Le Québécois - Thursday, March 1, 2007 - link
You said:But isn't it the same thing?
I mean mid-2007 is the 1st of july and Q3 also begins with july. Could you be more specific? Maybe the month we can expect them?
JarredWalton - Thursday, March 1, 2007 - link
Q3 means anywhere between July and late September, while mid-2007 means June or July time frame. As the official launch date approaches, we'll refine things where possible.Le Québécois - Thursday, March 1, 2007 - link
Thank you for your quick reply, as usual.mjrpes3 - Thursday, March 1, 2007 - link
Any word on when the desktop variant of Barcelona (Agena) will find its way into consumer's hands?puffpio - Thursday, March 1, 2007 - link
When you refer to DDR3 you call it DDDR3unless...there is a DDDR3 I don't know about?