Intel's Silverthorne Unveiled: Detailing Baby Centrino
by Anand Lal Shimpi on February 20, 2008 12:00 AM EST- Posted in
- CPUs
Who is Silverthorne?
In order to eventually compete in the ARM-space, Silverthorne has to be small and very cheap. The CPU itself is incredibly small thanks to its paltry 47M transistor count contributing to a die that's only 25 mm^2. Intel kept Silverthorne's die size small by greatly simplifying its architecture.
Silverthorne features a 16-stage in-order pipeline, meaning that it can only execute instructions in actual program order. This is different from Core 2, which can dynamically rearrange instructions in order to extract maximum parallelism from the code being worked on. By going with an in-order core, Intel reduces the complexity of the chip's design as well as reducing thermal output. Intel must balance the lack of instruction level parallelism that Silverthorne can extract with clever hardware and software tricks.
Remember Hyper Threading? Silverthorne will be the first Intel CPU since the Pentium 4 to allow the execution of two simultaneous threads on a single core. Silverthorne itself is too power hungry to be used in a dual-core design, and enabling two threads of execution yields a very efficient performance boost.
Since the CPU itself can't reorder instructions to help fill all available execution units, by allowing another thread of instructions to be dispatched simultaneously Intel increases the chances of fully utilizing all of Silverthorne's execution resources. Intel also trimmed the number of individual execution units on Silverthorne: SIMD and scalar integer multiplies are handled by the same unit, as are FP and integer divides.
Silverthorne can only issue two instructions per cycle, with the average IPC for most x86 applications at around 1 instruction the two thread design makes a lot of sense. Thankfully Silverthorne is being released into a world that is far more multithreaded than it was just a few years ago, otherwise such a design would hardly be sensible.
The 2-issue in-order design lessens the likelihood of being able to fill tons of execution units - so combining many functions into a single unit makes the most sense.
On the software side, Intel does do a lot in the compiler world which can come in handy, especially with Silverthorne. In-order processors shift the complexity of scheduling from the CPU to the compiler, meaning that while Silverthorne can run all x86 binaries, applications should be compiled for it in order to attain optimal performance.
Intel Core 2 (Penryn) | Pentium M (Dothan) | Silverthorne | |
L1 I-Cache | 32KB | 32KB | 32KB |
L1 D-Cache | 32KB | 32KB | 24KB |
L2 Cache | 6MB 24-way | 2MB 8-way | 512KB 8-way |
Pipeline Length | 14 | 12 stages | 16 stages |
x86 Decoding | 1 complex + 3 simple | 1 complex + 2 simple | 1 complex + 2 simple |
Maximum decode rate | 4+1 | 3 | 2 |
Issue ports | 6 | 5 | 4 |
FP Units | 1 FMUL and 1 FADD 1 FSTORE and 1 FLOAD | 1 FMUL or FADD | 1 FADD and 1 FMUL/SSE |
SSE Units | 3 | 1 | 1 |
Integer Units | 3 | 2 | 2 |
Manufacturing Process | 45nm | 90nm | 45nm |
Die Size | 107 mm^2 | 84 mm^2 | 25 mm^2 |
Transistor Count | 410M | 170M | 47M |
Release Date | 2H 2007 | 2H 2004 | 1H 2008 |
Silverthorne in many ways is similarly equipped to the old 90nm Pentium, but still falls short overall - performance shouldn't be better, but at least within the realm of competitive
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