The Nehalem Preview: Intel Does It Again
by Anand Lal Shimpi on June 5, 2008 12:05 AM EST- Posted in
- CPUs
A Quick Path to Memory
Our investigation begins with the most visibly changed part of Nehalem's architecture: the memory subsystem. Nehalem implements a very Phenom-like memory hierarchy consisting of small, fast individual L1 and L2 caches for each of its four cores and then a single, larger shared L3 cache feeding the entire chip.
Nehalem's L1 cache, despite being seemingly unchanged from Penryn, does grow in latency; it now takes 4 cycles to access vs. 3. The L2 cache is now only 256KB per core instead of being 24x the size in Penryn and thus can be accessed in only 11 cycles down from 15 (Penryn added an additional clock cycle over Conroe to access L2).
| CPU / CPU-Z Latency | L1 Cache | L2 Cache | L3 Cache |
| Nehalem (2.66GHz) | 4 cycles | 11 cycles | 39 cycles |
| Core 2 Quad Q9450 - Penryn - (2.66GHz) | 3 cycles | 15 cycles | N/A |
The L3 cache is quite possibly the most impressive, requiring only 39 cycles to access at 2.66GHz. The L3 cache is a very large 8MB cache, 4x the size of Phenom's L3, yet it can be accessed much faster. In our testing we found that Phenom's L3 cache takes a similar 43 cycles to access but at much lower clock speeds (2.0GHz). If we put these numbers into relative terms it takes 21.5 ns to get a request back from Phenom's L3 vs. 14.6 ns with Nehalem's - that's nearly 50% longer in Phenom.
While Intel did a lot of tinkering with Nehalem's caches, the inclusion of a multi-channel on-die DDR3 memory controller was the most apparent change. AMD has been using an integrated memory controller (IMC) since 2003 on its K8 based microprocessors and for years Intel has resisted doing the same, citing complexities in choosing what memory to support among other reasons for why it didn't follow in AMD's footsteps.
With clock speeds increasing and up to 8 cores (including GPUs) making their way into Nehalem based CPUs in the coming year, the time to narrow the memory gap is upon us. You can already tell that Nehalem was designed to mask the distance between the individual CPU cores and main memory with its cache design, and the IMC is a further extension of the philosophy.
The motherboard implementation of our 2.66GHz system needed some work so our memory bandwidth/latency numbers on it were way off (slower than Core 2), luckily we had another platform at our disposal running at 2.93GHz which was working perfectly. We turned to Everest Ultimate 4.50 to give us memory bandwidth and latency numbers from Nehalem.
Note that these figures are from a completely untuned motherboard and are using DDR3-1066 (dual-channel on the Core 2 system and triple-channel on the Nehalem system):
| CPU / Everest Ultimate 4.50 | Memory Read | Memory Write | Memory Copy | Memory Latency |
| Nehalem (2.93GHz) | 13.1 GB/s | 12.7 GB/s | 12.0 GB/s | 46.9 ns |
| Core 2 Extreme QX9650 - Penryn - (3.00GHz) | 7.6 GB/s | 7.1 GB/s | 6.9 GB/s | 66.7 ns |
Memory accesses on Conroe/Penryn were quick due to Intel's very aggressive prefetchers, memory accesses on Nehalem are just plain fast. Nehalem takes a little over 2/3 the time to complete a memory request as Penryn, and although we didn't have time to run comparable Phenom numbers I believe Nehalem's DDR3 memory controller is faster than Phenom's DDR2 controller.
Memory bandwidth is obviously greater with three DDR3 channels, Everest measured around a 70% increase in read bandwidth. While we don't have the memory bandwidth figures here, Gary measured a 10% difference in WinRAR performance (a test that's highly influenced by memory bandwidth and latency) between single-channel and triple-channel Nehalem configurations.
While we didn't really expect Intel to somehow do wrong with Nehalem's memory architecture, it's important to point out that it is very well implemented. Intel managed to change the cache structure and introduce an integrated memory controller while making both significantly faster than what AMD managed despite a four-year headstart.
In short: Nehalem can get data out of memory quick like bunnies.
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SiliconDoc - Monday, July 28, 2008 - link
lol- Buddy you are thinking.magreen - Thursday, June 5, 2008 - link
Thanks for the amazing preview, Anand!I hope you and Gary will get us more Nehalem information quick like bunnies.
yottabit - Thursday, June 5, 2008 - link
Great Article Anand! I'm so excited for this new technology. But that socket and triple channel memory archetecture makes me want to puke in my mouth a little bit. It's very reminiscent to me of the Socket 423/RDRAM era. I have the feeling that they are going to release this setup for a lot of the early adopters and then screw them over by dropping the socket completely, when they decide that Dual Channel DDR3 is fast enough. I can't picture two platforms running side by side, with two entirely different sockets. People whant a Nehalem but need 4 gigs of ram will end up buying 6 Gigs of ram... and DDR3 ain't exactly cheap.I wish they had plans to through this into the mainstream faster. I'd love to have one of these, in dual channel variety. I'm still running an old early A64, and I'm holding out for these next gen processors in the next year or two.
Its awesome to see that nice performance per clock increase, but the triple channel memory is a real slap in the face to me. Its like Intel saying "look, we increase clock for clock performance, but we also decided to use some brute force and raise our power consumption and motherboard complexity for no reason by adding another impractical memory channel". I don't see it as elegant at all. I think they are overcompensating for their lack of memory bandwith in recent times. :-
Maybe AMD will have a chance to jump in with some nicer Phenom's before Nehalem comes out and actually capture some quad core market?
npp - Thursday, June 5, 2008 - link
I'm tired of all those people who just can live with the fact that the world is spinning and the CPUs that were reviewed here are simply far faster than the Penryn or Phenom you just bought yesterday... Get used to the fact, this is how thing happen today. Nehalem will be probably the most advanced x86 (x64) CPU when launched, and it just happened that Intel developed it - it could have been anybody else, say AMD, or nVidia, or whoever you prefer, no difference to me. Things go ahead, and some vendors simply get the job done first, in the grand scheme of things, it is all the same. All those fanboys I see around sound like some 3 year old children fighting for candy to me, It's amusing to see how AMD or Intel PR locked you up, guys.Now a brief question, aimed directly at Anand, I guess: I still can't figure out why memory performance is so low even via an advanced controller such as Nehalem's. As far as I can tell, 3-channel DDR3-1066 should be able to deliver up to 25,5 GB/s of bandwidth, far from the figures we see. How does this happen? And once more: you measured some 46ms latency altogether, how was that obtained? Assuming memory clock of 133Mhz, this should yield something like CAS4 (~30ms) latencies for the memory, am I right?
fitten - Thursday, June 5, 2008 - link
30usAs far as single/dual/triple channel, it seems that Anand and gang were able to test with all three modes (you'll notice the comment about WinRAR being 10% faster with triple channel compared to single channel on the pre-release motherboard)... so you don't *have* to buy 3 sticks of memory... if you want 4GiB, you should be able to get 1x4 or 2x2 and leave the other slot(s) empty.
npp - Thursday, June 5, 2008 - link
It's all nanoseconds, of course, not milli- or micro, my fault. Never mind, I'm still awaiting some reasonable explanation about the "modest" bandwidth measured. 12GB/s copy is by no means little - I can't say if it's achievable via overclocking today, I'm not into that kind of business - but still I would guess no. Still, it seems little compared to the max. theoretical values.Anand Lal Shimpi - Thursday, June 5, 2008 - link
I think we may have to wait for a final Nehalem platform before we can make any calls on memory bandwidth figures, but do keep in mind that the amount of usable memory bandwidth will depend largely on how it's being measured. If the algorithm is even slightly compute bound we won't see perfect scaling with theoretical memory bandwidth.I'm not sure how Everest measures bandwidth so I can't tell you exactly what numbers we should be seeing there, but it is useful for comparing a relative increase in bandwidth between Penryn and Nehalem.
Take care,
Anand
npp - Thursday, June 5, 2008 - link
Thank you very much, very kind of you to bother answering my question! Keep up the good work here at Anandtech.NINaudio - Thursday, June 5, 2008 - link
I'm not sure hwy everyone is so concerned about DDR3 prices being high. A quick check shows that you can get a 2gig kit of ddr3-1600 for under $150 already. By the time Nehalem is out for mass consumption ddr3 will be even cheaper. I would say that it's pretty realistic to expect to be able to get a 3gig triple channel kit for under $100 and a 6gig triple channel kit for around $175 by the time nehalem is available to us.Anand Lal Shimpi - Thursday, June 5, 2008 - link
What I'm really interested in is why Intel felt that Nehalem needed a three channel DDR3 memory controller. Will it really be necessary for higher clocked Nehalem (or is it Nehalems)? It'd be great for the versions of Nehalem with integrated graphics but I figured those would mostly be pushed into the mainstream, dual channel SKUs anyways. Looks like we'll have to wait at least a few more months before we can find out for sure.-A